Delta-Sigma (ΔΣ) (or Sigma-Delta) modulation ADCs comprise a large family of ADCs used primarily to achieve high dynamic range through oversampling and filtering. In photography or other imaging technology, dynamic range is defined as a ratio of the maximum and minimum measurable light intensities. ΔΣ-ADCs are used almost exclusively when greater than 18 bits of resolution are needed for an application.
FIG. 1 schematically illustrates a conventional ΔΣ-ADC 100. Referring to FIG. 1, conventional ΔΣ-ADC 100 includes a Delta-Sigma Modulator (DSM) 110, a digital filter 120 electrically coupled to DSM 110, and a digital decimator 130 electrically coupled to digital filter 120. ΔΣ-ADC 100 receives analog input signal 10 and generates digital output signal 20 from decimator 130. As shown in FIG. 1, DSM 110 comprises a signal subtraction circuit 112, integrator 114, N-bit ADC 116, and N-bit feedback DAC 118.
DSM 110 allows a delayed version of the input signal 10 to pass therethrough, while subtracting a delayed version of the quantization error from the present quantization error (including uncorrelated noise). The delay in the output signal 20 and the subtracted quantization error constitutes a single sample time. As the sample rate increases with respect to the frequency of input signal 10, the delayed version of the quantization error approaches the current version of the quantization error and the difference between the two becomes very small. The error whose frequency is low enough for this to work is called in band noise. In this way, error is suppressed as sampling frequency increases while the signal is passed through with no compression. This noise suppression in the pass-band is called noise shaping.
In some implementations, DSM 110 can fit within an imaging pixel, with or without digital filter 120 and decimator 130. See, for example, U.S. Pat. No. 5,248,971, issued on Sep. 28, 1993 to Mandl. These modulators are very useful for creating image sensors with a high dynamic range. FIG. 2 illustrates a conventional DSM 200 which can be implemented completely inside an imaging pixel. See, for example, Boyd Fowler, CMOS Area Image Sensors with Pixel Level A/D Conversion, Ph.D. Dissertation, Stanford University, October 1995, at page 65 and FIG. 6.1. As shown in FIG. 2, in-pixel DSMs can comprise an integrator circuit 210 including an integration capacitor 215 (having a capacitance of Cint) that receives analog signals from an input circuit 205, a comparator (or single-bit ADC) 220, and a charge subtraction circuit (or single-bit DAC) 230.
ΔΣ digital pixel modulators have some useful features. The first feature is that DSM pixels are very compatible with Extended Counting. Extended Counting is a technique to pull out additional information from the charge left on integration capacitor 215 after the last modulator sample operation. This is adapted for ΔΣ image sensors using a first order modulator followed by a successive approximation residue conversion. See, for example, Christer Jansson, “A high-resolution, compact, and low-power ADC suitable for array implementation in standard CMOS,” IEEE Trans. on Cir. and Sys.-1: Fund. Theory and Apps., vol. 42, no. 11, November 1995. This approach has achieved 16 bits of resolution with 0.41 LSBs of noise without any trimming or correction.
Another useful feature is that the ΔΣ algorithm can filter or cancel comparator error from the operation of 1-b ADC 220, if there is a large number of samples or if Extended Counting is employed. This allows a much smaller and lower power comparator to be used as the decision circuit compared to some of the other high dynamic range modulation schemes used in-pixel, such as pulse frequency modulators (PFM). Comparators as simple as an inverter can be employed in the DSM pixel and still achieve good performance. The rejection of comparator error makes the ΔΣ circuit relatively immune to comparator power supply variation and even comparator decision level variation for large numbers of samples or with Extended Counting operation. The ΔΣ pixel's full-scale range must simply be large enough to contain the error without saturating or shutting off its components.
Another advantage of the ΔΣ digital pixel over some other modulators (e.g., pulse-frequency modulation or PFM) is its synchronous nature. At first glance, this might appear to be a disadvantage because PFM is capable of accepting extremely high input magnitudes, limited only by the oscillator's loop time constant or by practical issues, such as supply management and power consumption. However, the synchronous nature of the ΔΣ digital pixel allows many of the DSM components to be integrated outside the pixel. This allows the architecture to be used in much smaller pixels at the cost of synchronous array clocks running at the global or, as is more common, the row level.
In another implementation, an approach similar to FIG. 2 has been developed with the ADC circuitry being moved outside of the imaging pixel. See, for example, U.S. Pat. No. 5,659,315, issued on Aug. 19, 1997 to Mandl at FIGS. 13 and 15-17. This implementation still requires a similar charge subtraction circuit and a high gain transimpedance amplifier integrator to act as the modulator integrator and reference for the 1-b DAC.
Other more recent DSM approaches move most of the circuitry outside of the imaging pixel, except for a portion of the integrator and charge subtraction circuit, so as to reduce pixel size and power consumption. See, for example, U.S. Pat. No. 7,023,369, issued on Apr. 4, 2006 to Bocko et al. Instead of a fixed packet of charge transferred at high speed as shown in FIG. 2, the charge subtraction circuit in this approach is reconstructed to be a fixed current over the pixel access time. In this manner, the pixel size can be greatly reduced, but there are a number of key problems remaining with all of these approaches, which can be addressed by the circuit of the present disclosure.
DSMs are usually used to increase the dynamic range of image sensors. For many applications, they should be capable of integrating very high signal current in a short amount of time using a fast modulator sample rate. The circuit in FIG. 2 cannot operate nearly as fast as required by some applications. The 1-b DAC 230 is capable of pulling charge off the input node of amplifier 217 at very high speed, but amplifier 217 must work even faster to compensate for this high speed charge transfer or risk changing the bias on the detector too much. This detector bias spike may not be a problem for very high impedance silicon detectors, but it is a huge problem for infrared and scientific detector materials which may have very low impedance. These detectors produce vastly different signal currents under the same light conditions if the bias voltage across them changes too much. This is very difficult to calibrate out of an image and may severely limit performance of a sensor system.
The charge transfer mechanism of 1-b DAC 230 can also be problematic when there is a large array of modulators operating in parallel. The charge transfer circuit can reset in a closed-loop fashion, using PHI2, without disturbing the Gnd level very much. However, as soon as PHI1 closes to transfer charge off the integrator input node, the rush of current can cause a severe positive voltage spike in the ground connection. For this reason, some designs limit the current through the PHI1 charge transfer switch to help minimize this supply spike. This effect slows the rate at which the circuit can complete a charge transfer operation and places an upper limit on DSM sample rate. A slower sample rate may also prevent the circuit from working with very high signal levels over a very short integration time for a particular DSM resolution.
An array of DSMs working together may be clocked in a row-wise or column-wise fashion, with only a few rows or columns being clocked at once. This helps prevent supply spiking from all modulators trying to run a sample at one time. The clocks can scan through the array of modulators and complete a single sample clock cycle for all modulators. Each modulator has only a very short amount of time to complete its charge transfer operation before the clock is moved to a different group of modulators. This means that waiting for a controlled charge transfer in order to not spike Gnd or adversely bias the detector greatly slows down the maximum speed of the clock, limiting the minimum signal integration time. The modulator has much more time to reset the transferred charge mechanism than it does to actually perform the charge transfer.
The approach, as disclosed in U.S. Pat. No. 7,023,369 to Bocko et al., is targeted at reducing the circuit size to make the modulator compatible with small pixel image sensors. It partially solves the large array power consumption problem by keeping all active DC power consuming circuitry outside the pixel. However, it creates even bigger problems for high speed integration and high signals, because the integrated voltage must fully settle on high capacitance readout lines, which are shared by many pixels, in order to properly subtract a fixed amount of current from the accessed pixel. Signal subtraction schemes such as this using current as the subtracted signal over a fixed time interval (as opposed to charge transfer mechanisms) are also more susceptible to modulator clock jitter, because this jitter is directly injected into the magnitude of the subtracted signal. Running the modulator clock faster to achieve fast integration times for a given ADC resolution exacerbates this problem by increasing the magnitude effect of clock jitter on the subtracted signal magnitude. This uncertainty results in higher modulator noise and lower over-all signal-to-noise ratio for a particular modulator oversampling ratio.